The three-dimensional (3D) integration of two or more semiconductor structures can produce a number of benefits to microelectronic applications. For example, 3D integration of microelectronic components can result in improved electrical performance and power consumption while reducing the area of the device footprint. See, for example, P. Garrou, et al. “The Handbook of 3D Integration,” Wiley-VCH (2008).
The 3D integration of semiconductor structures may take place by the attachment of a semiconductor die to one or more additional semiconductor dies (i.e., die-to-die (D2D)), a semiconductor die to one or more semiconductor wafers (i.e., die-to-wafer (D2W)), as well as a semiconductor wafer to one or more additional semiconductor wafers (i.e., wafer-to-wafer (W2W)), or a combination thereof.
Several process sequences have been developed to facilitate the formation of 3D integrated semiconductor structures, including, for example, electrical connection between individual semiconductor structures, thinning of one or more of the semiconductor structures and alignment and bonding of individual semiconductor structures, etc. In particular, thinning of the one or more semiconductor structures comprising the 3D integrated semiconductor structure may be employed for a number of reasons, including, for example, improved heat dissipation and reduction of electrical resistance. However, the benefits that may be produced by thinning of the one or more semiconductor structures comprising the 3D integrated semiconductor structure may also introduce process complications, for example, a semiconductor structure may become relatively brittle due to a thinning process and may, thus, be susceptible to cracking, fracture or other damage during processing using existing equipment and materials.
One proposed solution to this problem is to bind the semiconductor structure, such e.g., such as a semiconductor wafer, to a reinforcing substrate, such as another wafer (e.g., a carrier wafer) to provide mechanical strength during processing (e g., thinning) of the semiconductor wafer. The process of bonding the semiconductor wafer to the reinforcing substrate is often referred to as “wafer bonding.” After processing the semiconductor wafer, the reinforcing substrate may be released from the semiconductor.
For example, a semiconductor wafer may be temporarily bonded to a reinforcing substrate using an adhesive material. The adhesive material bears the force associated with holding the semiconductor wafer and the reinforcing substrate together during processing of the semiconductor wafer. Furthermore, the adhesive material and the reinforcing substrate may function as a mechanical support to provide structural stability to the semiconductor wafer during processing of the semiconductor wafer. Many spin-coated amorphous polymers, such as polyimides, benzocyclobutene (BCB), NAFION® and photoresist materials have been used as adhesive materials for wafer bonding.
Adhesive materials may be unstable at increased temperatures, however, which may limit the temperatures at which semiconductor device fabrication may be conducted. Furthermore, solvent or solvent vapors may be released from such adhesive materials at elevated temperatures. This process is often referred to as “outgassing.” Outgassing may result in the formation of bubbles or voids in the adhesive material. Such bubbles or voids may result in non-uniform bonding strength between the semiconductor wafer and the reinforcing substrate, and may compromise the integrity of the bond. The adhesive material is completely removed after semiconductor wafer processing using a chemical removal process (e.g., dissolving in a solvent). The chemical removal process may be time-consuming and damaging to semiconductor devices and integrated circuit devices formed on the semiconductor wafer. Thus, adhesive bonding may be problematic when used in temporarily bonding a semiconductor wafer to a reinforcing substrate.
Another method of providing support for a semiconductor wafer during processing involves directly bonding two semiconductor substrates using a so called “direct” wafer bonding process. Direct wafer bonding processes are conventionally used in forming semiconductor-on-insulator (SeOI) structures (e.g., silicon-on-insulator (SOI) structures) that are of interest for fabrication of advanced ICs for three-dimensional (3D) device integration. In a conventional direct wafer bonding process a surface oxide layer may be formed over at least one of the wafers. The surface oxide layer may then be bonded to a silicon material or another oxide material on a surface of the other wafer. For example, a surface of an oxide material on a semiconductor wafer may be contacted with a surface of a reinforcing substrate and the two structures may be bonded together via atomic and/or molecular adhesion. To achieve a bond between two semiconductor wafers, the semiconductor wafers should have low surface roughness compatible surface chemistries (i.e., hydrophilicity and hydrophobicity), and should be at least substantially free of dust and other debris.